Self-adjusting hold-off trigger

ABSTRACT

A self-adjusting hold-off trigger circuit and method detects a threshold crossing between consecutive samples of a digitized input signal as edge events, identifies the crossing as a qualified trigger event if the crossing is in a desired direction based upon trigger criteria, and provides a trigger output when the qualified trigger event occurs greater than an approximate average or peak time after a preceding edge event.

CROSS-REFERENCE TO RELATED APPLICATIONS

The current application is a non-provisional application based upon andclaiming the filing date under 35 U.S.C. 119(e) of provisionalapplication Ser. No. 60/835,562, filed on Aug. 3, 2006, whichprovisional application is abandoned upon the filing of thisnon-provisional application.

BACKGROUND OF THE INVENTION

The present invention relates to acquisition of an input signal, andmore particularly to a self-adjusting hold-off trigger for anacquisition system which is based on approximate time between triggerlevel crossings by the input signal.

U.S. Pat. No. 7,072,804, issued to Dennis J. Weller on Jul. 4, 2006,discloses a digital trigger circuit having an input filter for producinglow and high frequency rejection trigger signals, as well as AC and DCtrigger signals, derived from a digitized input signal. One of the fourtrigger signals is selected by a multiplexer and input to a triggercomparator having an upper trigger level and a lower trigger level toprovide a desired amount of hysteresis, one trigger level being adesired trigger level and the other being a hysteresis level.

The hysteresis in the trigger comparator provides a noise rejectionfunction. Low levels of noise are ignored. For rising edge triggerevents, without hysteresis the noise may cause the falling edge of thedigitized input signal to be detected as a rising edge. As shown in FIG.1 a rising edge is detected on the transition from point A to point B.Without hysteresis other rising edges are detected on the transitionsfrom point C to point D and again from point K to point L. A measurementinstrument operator, attempting to trigger on rising edges, gets annoyedwhen the measurement instrument triggers on the transition from point Kto point L, since this is clearly part of an overall falling edge. Whenthe horizontal display scale is such that points J, K, L and M all occurwithin the same display column, the presence of a rising edge is notvisible, and it appears that the acquisition system trigger circuit ismalfunctioning. By adding hysteresis in the trigger comparator, asshown, the trigger circuit no longer triggers on the transition frompoint K to point L. A rising trigger edge only happens after the signalhas passed below the hysteresis level and then passes above the desiredtrigger level.

Unfortunately a trigger comparator with hysteresis waits until the inputtrigger signal has passed above or below both levels (depending uponwhether triggering is on the rising or falling edge of a signal) so thatit doesn't mistakenly trigger on noise. When a state machine, whichgenerates a trigger from the output of the trigger comparator, is set upfor pulse width triggering, this may result in an error since themeasured width from above the high level to below the low level may notaccurately reflect the pulse width at the desired trigger level. Alsorising edge trigger events stop occurring when the trigger level is nearthe minimum peak value for the digitized input signal, and falling edgetrigger events stop occurring when the trigger level is near the maximumpeak value for the digitized input signal.

U.S. Pat. No. 4,771,193, issued to Genichiro Ohta on Sep. 13, 1988 showsan analog circuit for triggering on a maximum length pulse within aninput signal. As shown in FIG. 2 of the '193 patent, an input digitalsignal (a) produces a ramp signal (b) for each pulse, the height of theramp being a function of the width of the pulse. A capacitor is charged,as shown by signal (c), and enables a sweep (I) that starts at theconclusion of the longest pulse. In this way the measuring instrumenttriggers on a non-signal interval indicated by the longest pulse width.This trigger circuit operates on a peak detection basis, i.e.,triggering on the highest peak of the ramp signal (b).

U.S. Pat. No. 5,223,784, issued to Theodore G. Nelson, et al on Jun. 29,1993, shows a circuit for triggering an acquisition system only onceduring a period of an input signal. A first trigger comparator detectsqualifying trigger events in an input signal using a first referencetrigger level, which qualifying trigger events charge a capacitor. Asecond trigger comparator compares the voltage on the capacitor with asecond reference trigger level, and produces a pulse if the capacitorvoltage has a predetermined relationship to the second reference triggerlevel. Subsequent trigger events which occur before a predeterminedperiod of time, determined by an RC time constant, are unable to produceanother trigger event.

The above-discussed patents are analog trigger circuit implementations.With the current digital storage oscilloscopes digital trigger circuitimplementations are generally desired. Also these patents do notconsider measuring an average duration between threshold crossings andthen triggering only when a potential trigger event is preceded by atime related to the average duration.

What is desired is a self-adjusting hold-off trigger that uses anapproximate time based upon average or peak time or duration between aqualified trigger event and a preceding edge event.

BRIEF SUMMARY OF THE INVENTION

Accordingly the present invention provides a self-adjusting hold-offtrigger circuit that detects a threshold crossing between consecutivesamples of a digitized input signal as edge events, identifies thecrossing as a qualified trigger event if the crossing is in a desireddirection based upon trigger criteria, and provides a trigger outputwhen the qualified trigger event occurs greater than an approximateaverage or peak time after a preceding edge event.

The objects, advantages and other novel features of the presentinvention are apparent from the following detailed description when readin conjunction with the appended claims and attached drawing.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a graphic view of a noisy digitized input signal as processedby a trigger comparator having hysteresis according to the prior art.

FIG. 2 is a block diagram view of an illustrative self-adjustinghold-off trigger circuit according to the present invention.

FIG. 3 is a flow diagram view for a self-adjusting hold-off triggermethod using approximate average time according to the presentinvention.

FIG. 4 is a flow diagram view for a self-adjusting hold-off triggermethod using approximate peak time according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention has a trigger comparator that does not usehysteresis, so for the digitized signal of FIG. 1 the trigger comparatoroutput observes all rising and falling trigger events, i.e., eachcrossing of a desired trigger level—only one trigger level is used.Therefore there is a rising trigger event on the transition from point Ato point B; a falling trigger event on the transition from point B topoint C; a rising trigger event on the transition from point C to pointD; a falling trigger event on the transition from point J to point K; arising trigger event on the transition from point K to point L; and afalling trigger event on the transition from point L to point M. Aself-adjusting hold-off trigger circuit, as described below with respectto FIG. 2, measures the time between trigger events and computes anapproximation of an average or peak time between trigger events. Atrigger event is used for triggering signal acquisition when the timebetween a current qualified trigger event and a preceding trigger eventis greater than the approximate average or peak time. Also only triggerevents in a specified direction, such as rising trigger events, are usedas qualified trigger events.

Referring now to FIG. 2 the digitized input signal is compared with athreshold level in a digital comparator 12, which converts the digitizedinput signal to a binary signal—values above the threshold are given alogical value of “1” and values below the threshold are given a logicalvalue of “0”. Referring to FIG. 1 the output of the comparator for aportion of the digitized signal becomes “1110100000000101111111010”ending with point M, as shown by the comparator output withouthysteresis. The binary signal is input to a flip-flop 14 which isclocked by a sample clock. The output and input of the flip-flop 14 arecompared by an XOR gate 16 to provide a control signal for a firsttiming multiplexer 18, which control signal is indicative of a binarytransition or crossing of the trigger level or threshold between samplesof the input signal. Also the inverted output from the flip-flop 14 isinput to an AND gate 20 together with the binary signal. The AND gate 20is used to detect a desired crossing direction for the binary signal,i.e., a transition from “0” to “1” indicative of a rising edge for thedescribed embodiment. In other words the output of the AND gate 20provides qualified trigger events—trigger events that satisfy a desiredtrigger criteria such as rising edges in this example.

For each threshold crossing detected by the XOR gate 16, the firsttiming multiplexer 18 selects a constant value—“0” (as shown) or “1”depending upon a desired starting count value. The value from the firsttiming multiplexer 18 is loaded into a time register 22 each sampleclock cycle, the output of which is coupled to a maximum time comparator24 that is used to prevent the time value from getting too large in theevent the input signal has a significant drop-out period. If the timestored in the time register 22 exceeds the maximum value applied to themaximum time comparator 24, then a second timing multiplexer 26 selectsa “zero” increment for adding back to the time register via an adder 28.The output from the maximum time comparator 24 may also be used toprovide a flag to a user that there is a gross error in the inputsignal. Otherwise the second timing multiplexer 26 selects a “one”increment for input to an adder 28 to increase the time value stored inthe time register 22 via the first timing multiplexer 18. Thus the timeloop increments the time value in the time register 22 each sample clockcycle so long as there is no trigger level crossing detected; resets thetime value for each detected trigger level crossing; and keeps the timevalue from exceeding a predetermined maximum value.

The time value from the time register 22 also is input to a subtractor30 where a current average value from an average register 32 issubtracted from the time value. The result from the subtractor 30 isadjusted in a first multiplier 34 by a first factor, n, and added to thecurrent average value in an average adder 36. The average value and theoutput from the average adder 36 are input to a second multiplexer 38.The output from the second multiplexer 38 is determined by the directionsignal from the AND gate 20. If there is no rising edge, then thecurrent average value is transferred back into the average register 32.If there is a rising edge, then the updated average value from theaverage adder 36 is loaded into the average register 32. The averagevalue from the average register 32 is multiplied (40) by a secondfactor, k, and applied as an approximate average level to an outputcomparator 42. Also input to the output comparator 42 is the time valuefrom the time register 22. The output comparator 42 provides an enablesignal to an output AND gate 44. Also input to the output AND gate 44 isthe direction signal from the AND gate 20. When a rising edge occurs andthe time value representing time from the preceding edge of thedigitized input signal exceeds the approximate average value, the outputAND gate 44 provides a trigger event for signal acquisition. Thefactors, n and k, generally have a value between zero and one.

Although the above description applies to a rising edge trigger circuit,appropriate modifications may be made to produce a falling edge triggercircuit. Also where multiple pipes of samples resulting fromoversampling of the input signal to produce multiple samples per sampleclock are used, the process described above may be readily applied.Further trigger events may be implemented that use more complexqualifiers, such as a specific pulse width, a serial data packet, etc.For these higher level qualifiers, the hold-off may be adjusted at thishigher level, i.e., triggering when the average time between serial datapackets between devices exceeds the average, or the like.

The basic concept is further illustrated by the flow diagram of FIG. 3where each sample is processed in turn. A current acquired sample, step50, is tested to determine whether the trigger level or threshold hasbeen crossed from an immediately previous sample, step 51. If thetrigger level is not crossed by the current sample, then the time isincremented, step 52, and the next sample is acquired from the inputsignal, step 50. If the threshold is crossed, the direction of thecrossing (rising or falling) is tested, step 53, depending upon whetherthe trigger circuit is configured for triggering on rising or fallingedges. If the crossing is in the wrong direction, then the time isreset, step 54, and the next sample acquired, step 50. Otherwise thecurrent time value is tested, step 55, to determine whether it exceedsan approximate average value. If the approximate average is notexceeded, then the average is updated by the current time, step 56, andtime is reset, step 54, for acquisition of the next sample, step 50. Ifthe approximate average is exceeded, then a trigger event is output,step 57, the average is updated, step 56, and the time is reset, step54, for the next sample acquisition, step 50. The update average step 56illustratively may be:AVERAGE=AVERAGE+(TIME−AVERAGE)/8where n=⅛.

A similar algorithm may be used to use peak time values rather thanaverage time values as the trigger criteria, as shown in FIG. 4, so thattriggering occurs on the peak interval values of the input signal. Inthis case time is compared to an approximate peak time value, step 65,rather than an approximate average time value. If the approximate peaktime value is not exceeded, then the peak time value is reduced, step66, such as PEAK=PEAK*n. Otherwise the trigger event is output, step 57,the peak time value is set to the current time value, step 68, and timeis reset, step 54. In this way the peak time value represents thelongest interval between qualified trigger events.

Thus the present invention provides a self-adjusting hold-off trigger bydetecting each crossing of a trigger level by a digitized input signalas edge events, qualifying each edge event as a qualified trigger eventif the crossing is in the desired direction, and generating a triggeroutput when a qualified trigger event occurs that exceeds an average orpeak time from a preceding edge event.

1. A method of generating a self-adjusting hold-off trigger comprisingthe steps of: generating qualified trigger events from a digitized inputsignal based upon threshold crossings by the digitized input signal andupon trigger criteria; providing a trigger output for acquiring thedigitized input signal for each of the qualified trigger events thatoccurs greater than an approximate time after an immediately precedingthreshold crossing; and updating the approximate time after eachqualified trigger event.
 2. The method as recited in claim 1 wherein theupdating step comprises the steps of: determining a time between eachqualified trigger event and the immediately preceding thresholdcrossing; and averaging the times to produce an average time betweenqualified trigger events and immediately preceding threshold crossingsas the approximate time.
 3. The method as recited in claim 2 wherein theupdating step further comprises the step of multiplying the average timeby a factor to produce the approximate time.
 4. The method as recited inclaim 1 wherein the updating step comprises the steps of: determining atime between each qualified trigger event and the immediately precedingthreshold crossing; and setting a peak time value equal to the time whenthe trigger output produced in the providing step, the peak time valuebeing the approximate time.
 5. The method as recited in claim 4 whereinthe updating step further comprises the step of reducing the peak timevalue by a factor to produce the approximate time.
 6. A self-adjustinghold-off trigger apparatus comprising: means for determining qualifiedtrigger events from a digitized input signal based upon thresholdcrossings and upon trigger criteria; means for providing a triggeroutput for acquiring the digitized input signal for each of thequalified trigger events that occurs greater than an approximate timeafter an immediately preceding threshold crossing; and means forupdating the approximate time after each qualified trigger event.
 7. Theapparatus as recited in claim 6 wherein the updating means comprises:means for determining a time between each qualified trigger event andthe immediately preceding threshold crossing; and means for averagingthe times to produce an average time between qualified trigger eventsand immediately preceding threshold crossings as the approximate time.8. The apparatus as recited in claim 7 wherein the updating meansfurther comprising means for multiplying the average time by a factor toproduce the approximate time.
 9. The apparatus as recited in claim 6 theupdating means comprises: means for determining a time between eachqualified trigger event and the immediately preceding thresholdcrossing; and means for setting a peak time value equal to the time whenthe trigger output produced in the providing step, the peak time valuebeing the approximate time.
 10. The apparatus as recited in claim 9wherein the updating means further comprises means for reducing the peaktime value by a factor to produce the approximate time.
 11. Aself-adjusting hold-off trigger apparatus comprising: a thresholddetector and qualifier circuit having as inputs a digitized input signaland a threshold level, and having as outputs edge events indicative ofthe digitized input signal crossing the threshold level and qualifiedtrigger events corresponding to the edge events that meet triggercriteria; a timing loop having as inputs the edge events from thethreshold detector and a reset constant, and having as an output a timebetween edge events wherein the time is returned to the reset constantat each edge event and periodically increased by a selected incrementbetween edge events; an approximate time update circuit having as inputsthe qualified trigger events and the time from the timing loop, andhaving as an output an approximate time that is a function of theinputs; and an output circuit having as inputs the time from the timingloop, the approximate time and the qualified trigger events, and havingas an output a trigger event for acquiring the digitized input signalfor each qualified trigger event where the time from the timing loopexceeds the approximate time.
 12. The apparatus as recited in claim 11further comprising a maximum time logic having as inputs the time fromthe timing loop, a maximum time value and a plurality increments, andhaving as an output a selected one of the increments as the selectedincrement for the timing loop, the selected increment being zero whenthe time exceeds the maximum time value to hold the time at the maximumtime value until a next one of the edge events is output from thethreshold detector and qualifier circuit.